1. Field of the Invention
The present invention relates to electrically erasable programmable read-only nonvolatile semiconductor memory (EEPROM).
2. Description of the Related Art
Conventionally, an electrically erasable programmable read-only memory (EEPROM), which electrically performs data write-in and erasure, for example, has been known as a nonvolatile semiconductor memory (Non Patent Reference 1: R. Shirota, ‘A Review of 256-Mbit NAND Flash Memories and NAND Flash Future Trend’, Non-Volatile Semiconductor Memory Workshop (NVSMW) 2000, p. 0.22-31). In this EEPROM, especially a NAND type, a memory cell array is configured by disposing memory cells at the respective intersections of horizontal word lines and vertical bit lines. A MOS transistor having a ‘stacked gate structure’ configured by stacking a floating gate (FG) and a control gate (CG), for example, is typically used as a memory cell.
There are a number of conventional methods for forming the gate electrode of a select gate transistor such as electrically connecting a floating gate and a control gate by etching a part of the inter-gate insulating film of the select gate transistor. However, with any of these methods, as miniaturization progresses, processing becomes difficult when the floating gate is particularly a thin film.